Semiconductor dies often need to be identified for a variety of reasons, including, but not limited to, tracking dies during manufacturing, tracking die inventories, determining the date upon which a particular die or group of dies was manufactured, determining the particular manufacturing batch corresponding to a particular die, and so on. Identification information ideally permits a particular semiconductor die, either during or after manufacturing, to be identified with 100% confidence. Once a particular die has been identified, other information pertaining to the die may be retrieved or used, such as the die's date of manufacture, manufacturing batch information associated with the die, the date the die was shipped from the foundry, royalty information associated with the die, and other information.
Most current semiconductor die identification methods use non-volatile storage elements, such as RFID tags, fuses or non-volatile memories to store die identification information or tags. These methods generally require that additional circuitry for storing such information be incorporated into the die. They also generally involve extra tasks such as programming non-volatile elements. As a result, prior art die identification methods can involve considerable costs due to the need to provide extra circuitry and extra test and programming time.
One example of a prior art method of identifying semiconductor dies is provided by SiidTech Inc. of Hilsboro, Oreg., who employ “silicon fingerprinting technology” to trace semiconductor dies, and incorporate such technology into RFID circuits, smart cards and badges and hardware keys. Still other applications include tagging, authentication and intellectual property tagging.
Various patents containing subject matter relating directly or indirectly to the field of the present invention include, but are not limited to, the following:
U.S. Pat. No. 6,161,213 for System for providing an integrated circuit with a unique identification to Lofstrom.
U.S. Pat. No. 5,051,895 for Apparatus and method for tracking and identifying printed circuit assemblies to Rogers.
U.S. Pat. No. 5,079,725 for Chip identification method for use with scan design systems and scan testing techniques to Geer at al.
U.S. Pat. No. 5,301,143 for Method for identifying a semiconductor die using an IC with programmable links to Ohri et al.
U.S. Pat. No. 5,350,715 for Chip identification scheme to Lee.
U.S. Pat. No. 5,553,022 for Integrated circuit identification apparatus and method to Weng et al.
U.S. Pat. No. 5,642,307 for Die identifier and die identification method to Jernigan.
U.S. Pat. No. 5,742,526 for Apparatus and method for identifying an integrated device to Voshell et al.
U.S. Pat. No. 5,818,738 for Method for testing the authenticity of a data carrier having an integrated circuit to Effing et al.
U.S. Pat. No. 5,895,962 for Structure and a method for storing information in a semiconductor device to Zheng et al.
U.S. Pat. No. 6,147,316 for Method for sorting integrated circuit devices to Beffa.
U.S. Pat. No. 6,190,972 for Method for storing information in a semiconductor device to Zheng et al.
U.S. Pat. No. 6,365,421 for Method and apparatus for storage of test results within an integrated circuit to Debenham et al.
U.S. Pat. No. 6,601,008 for Parametric device signature to Madge.
U.S. Pat. No. 6,710,284 for Laser marking techniques for bare semiconductor die to Farnworth et al.
U.S. Pat. No. 6,812,477 for Integrated circuit identification to Matsunami.
U.S. Pat. No. 6,813,058 for Method and apparatus for personalization of semiconductor to Sandstrom.
U.S. Pat. No. 6,830,941 for Method and apparatus for identifying individual die during failure analysis to Lee at al.
U.S. Pat. No. 6,889,305 for Device identification using a memory profile to Andelmann.
U.S. Pat. No. 6,941,536 for Method for identifying semiconductor integrated circuit device, method for manufacturing semiconductor integrated circuit device, semiconductor integrated circuit device and semiconductor chip to Muranaka.
U.S. Pat. No. 6,960,753 for Photosensor arrays with encoded permanent information to Cheung.
U.S. Pat. No. 6,990,387 for Test system for identification and sorting of integrated circuit devices to Freij et al.
U.S. Pat. No. 6,944,567 for Method in an integrated circuit (IC) manufacturing process for identifying and redirecting ICs mis-processed during their manufacture to Beffa.
U.S. Pat. No. 6,996,484 for Sequential unique marking to Raitter.
U.S. Pat. No. 7,015,795 for Self-identifying integrated circuits and method for fabrication thereof to Doudoumopolous.
U.S. Pat. No. 7,017,043 for Methods and systems for the identification of circuits and circuit designs to Potkonjak.
What is needed is a method and device for tracking semiconductor dies during and after manufacturing that is accurate and inexpensive, and that does not require additional circuitry on, or additional programming of, the dies. Upon having read and understood the Summary, Detailed Descriptions and Claims set forth below, those skilled in the art will appreciate that at least some of the devices and methods disclosed in the printed publications listed herein may be modified advantageously in accordance with the teachings of the present invention.